JESD22 A114F PDF

JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. By downloading this file the individual agrees not to charge for or resell the resulting material. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement.

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JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes.

The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met.

By downloading this file the individual agrees not to charge for or resell the resulting material. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. The objective is to provide reliable, repeatable HBM ESD test results so that accurate classifications can be performed.

The simulator must be capable of supplying pulses with the characteristics required by Figure 2 and Figure 3. The probe transformer and cable with a nominal length of 1 meter shall have a 1 GHz bandwidth, a minimum current rating of 12 amperes peak pulse-current capability and a rise time of less than one nanosecond.

The lead length should be as short as practicable to span the distance between the two farthest pins in the socket while passing through the current probe. The ends of the wire may be ground to a point where clearance is needed to make contact on fine-pitch socket pins.

A ? Precautions must be taken in tester design to avoid recharge transients and multiple pulses. NOTE 3 R2, used for initial equipment qualification and requalification as specified in 3.

NOTE 6 S2 shall be closed at least 10 milliseconds after the pulse delivery period to ensure the DUT socket is not left in a charged state. A voltage probe with a minimum input impedance of 10M? A 10k? A Zener diode with breakdown voltage between 6 V and 15 V and a rating between? Recalibration is required whenever equipment repairs are made that may affect the waveform and a minimum of every 12 months. The tester must meet the requirements of Table 1 and Figure 2 at all voltage levels, except V, using the shorting wire and at the V and V levels with the ?

The V level is optional. The waveform measurements during calibration shall be made using the worst-case pin on the highest pin count board with a positive mechanical clamp socket. Machine repeatability should be verified during initial equipment acceptance by performing a minimum of 5 consecutive positive and a minimum of 5 consecutive negative waveforms at a voltage level in Table 2.

This test will check for any open or short relays. When the optional shunt resistance as specified in 3. Additionally, all personnel shall receive system operational training and electrical safety training prior to using the equipment. Some advanced technologies may be vulnerable to these pulses resulting in an electrical overstress EOS.

Scanning for the presence of any trailing pulse shall cover a period of at least 1 msec after the HBM pulse. This part of the slow decay shall be excluded in determining the trailing pulse magnitude. NOTE 2 To determine if a device to be tested is susceptible to damage from the trailing pulse it may be necessary to measure the voltage across the actual device during HBM testing, or a circuit similar to that in Figure 4.

The measured voltage and the time that it is present on the device can then be compared to the known reliability mechanisms of the technology, such as time dependent dielectric breakdown TDDB , to determine if a reliability concern is posed by the HBM tester. The characteristics of this pre-pulse phenomenon depend on the conditions and the environment of the arcing associated with the HBM discharge, the parasitic capacitances of the tester, as well as the pin impedance of the device under test.

Due to lack of specifications for this phenomenon, the magnitude of the resulting voltage rise at the stressed pin may vary significantly from tester to tester and can alter the behaviors of some ESD protection circuits.

The tester-dependent voltage rise was observed to alter the timing of the protection action. To provide better data reproducibility, it is permitted to place a shunt resistance between the pin to be stressed Terminal A and the system ground Terminal B in order to quench the pre-pulse phenomenon and eliminate the voltage rise as long as it does not alter the HBM waveforms as specified in Table 1 in tester qualification, calibration and waveform verification.

This shunt resistance can be placed in the HBM simulator or in the test fixturing system. A resistance value of 10 kohm or larger is recommended. It is recommended that the manufacturers supply the worst-case pin data with each DUT board.

The pin combination with the waveform closest to the limits see Table 1 shall be designated for waveform verification. Connect this pin to Terminal B where it will remain the referenced pin throughout the worst-case pin search and connect one of the remaining pins to Terminal A. Attach a shorting wire between these pins with the current probe around the shorting wire, as close to Terminal B as practicable. Apply a positive and negative V pulse and verify that the waveform meets the requirements defined in Table 1.

NOTE As an alternative to the worst-case pin search, the reference pin pair may be identified for each test socket of each test fixture. The reference pin combination shall be identified by determining the socket pin with the shortest wiring path from the pulse generating circuit to the test socket.

Connect this pin to Terminal B and then connect the socket pin with the longest wiring path from the pulse generating circuit to the test socket to Terminal A normally provided by the manufacturer.

Attach a shorting wire between these pins with the current probe around the shorting wire. Follow the procedure in step 3. For the initial board check-out connect a ?

Apply a positive and negative V pulse and verify the waveform meets the requirements defined in Table 1. If at any time the waveforms do not meet the requirements defined within Figure 2 and Table 1 at the V or V level, the testing shall be halted until the waveform is in compliance.

Additionally, the system diagnostics test as defined in 3. The period between waveform checks may be extended providing test data supports the increased interval. In case the waveform no longer meets the limits in Table 1, all ESD testing performed after the previous satisfactory waveform check will be considered invalid.

Place the current probe around the shorting wire. Verify that all parameters meet the limits specified in Table 1 and Figure 2. Testing must be performed using an actual device chip. It is not permissible to use a test chip representative of the actual chip or to assign threshold voltages based on data compiled from a design library or via software simulations.

Guard band testing is also permitted. The test devices shall be within the limits stated in the part drawing for these parameters. Finer voltage steps may optionally be used to obtain a more accurate measure of the failure threshold. ESD testing should begin at the lowest step in Table 1 but may begin at any level. However, if another higher starting voltage level is used and the device fails, testing shall be restarted with a fresh device at the next lowest level.

The ESD test shall be performed at room temperature. Longer intervals are permitted and should be used if the devices are expected to be vulnerable to cumulative effects. It is permitted to use a separate sample of 3 devices for each pin combination set specified in Table 2.

It is permitted to further partition each pin combination set in Table 2 and use a separate sample of 3 devices for each subset within the pin combination set. It is permitted to use the same sample 3 at the next higher voltage stress level if all parts pass the failure criteria specified in clause 5 after ESD exposure to a specified voltage level.

The actual number of pin combination sets depends on the number of power pin groups. Power pins and Power Pin Groups are defined in 4. Active discrete devices FETs, transistors, etc. All pins which are not connected to the die shall be verified as such and left open floating at all times.

When replacing only a single polarity of a given combination, the opposite polarity shall be used when adopting this reverse pin combination alternative. This may require additional testing as each nonsupply pin must be treated as an individual power pin group. The number of power pins tested on Terminal A may be reduced if the power pin group is connected on a package plane see clause 4.

Power pins that are directly connected by metal inside the package form a power pin group. The other pins in the group do not need to be stressed. In the test sequences where this power pin group is held at ground Terminal B , it is permitted to have all the pins in the group tied together and connected to Terminal B or to have only the previously selected pin s connected to Terminal B with all other pins in the group left floating.

Any pin that is connected to an internal power bus or a power pin by metal must be treated as a power pin example: a Vdd sensing pin. In that case, the pin may be tied together with the power pin s connected to the same bus and treated as one pin for Terminal B connection even though it is labeled a different name. Any pin that is intended to supply power to another circuit on the same chip must be treated as a power pin.

However, if a pin intended to supply power to a circuit on another chip but not to any circuit on the same chip, it may be treated as a signal pin.

As an alternative to this method, it is permitted to partition the pins to be connected to terminal B into two or more subsets, such that each of these pins is a member of at least one subset. The pin connected to terminal A is to be stressed to each of these subsets separately.

If testing is required at multiple temperatures, testing shall be performed at the lowest temperature first. This issue may impact slew rate triggered ESD protection methods on higher pin count packages.

This tester issue was found to divert significant current away from the pins connected to Terminal B, such that the slew-rate of the current at terminal B is lower than seen at Terminal A.

Due to this effect the current waveform seen at Terminal B would not match the one seen using a non-relay, 2-pin HBM test between the same set of pins. Example of proposed changes being utilized Test Flow 1 HBM testing will be done in adherence to Table 2, with selected pin combinations replaced by alternative pin combinations.

If the Supply pins are connected on package plane clause 4. Other pins in the group do not need to be stressed. For Example: pin Product with following pin information:? Vdd1: 8 pins shorted on die only? Vdd2: 8 pins shorted on die only? Vdd3: 24 pins shorted in package? Gnd1: 8 pins shorted on die only? Gnd2: 8 pins shorted on die only? Gnd3: 24 pins shorted in package? HBM Test plan would as follows: 1.

All pins one at time to Gnd1 power pin group 2.

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JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met.

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