This section summarises the enhancements of the 2 nd generation device compared to its FT8UAM predecessor. For further details, consult the device pin-out description and functional descriptions. The existing RESET pin is maintained in order to allow external logic to reset the device where required, however for many applications this pin can now simply be hard wired to VCC. This circuit is now embedded on-chip — the pin assigned to this function is now designated as the TEST pin and should be tied to GND for normal operation.

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This device not only adds extra functionality to its FT8UAM predecessor and reduces external component count, but also maintains a high degree of pin compatibility with the original, making it easy to upgrade or cost reduce existing designs as well as increasing the potential for using the device in new application areas.

Single Chip USB? Asynchronous Serial Data Transfer? Future Technology Devices Intl. For further details, consult the device pin-out description and functional descriptions.

The existing RESET pin is maintained in order to allow external logic to reset the device where required, however for many applications this pin can now simply be hard wired to VCC. This circuit is now embedded on-chip — the pin assigned to this function is now designated as the TEST pin and should be tied to GND for normal operation.

For applications where scheduling latency takes priority over data integrity such as transferring audio and low bandwidth video data, the new device now offers an option of USB Isochronous transfer via an option bit in the EEPROM.

In this mode, any residual voltage on external circuitry is bled to GND when power is removed thus ensuring that external circuitry controlled by PWREN resets reliably when power is restored. DSBL Version 1. Programmable Receive Buffer Timeout In the previous device, the receive buffer timeout used to? This timeout is now programmable over USB in 1ms increments from 1ms to ms, thus allowing the device to be better optimised for protocols requiring faster response times from short data packets.

TXDEN now works correctly during a transmit send-break condition. Relaxed VCC Decoupling The 2 generation devices now incorporate a level nd to the device and they will be sequentially sent to the interface at a rate controlled by the prescaler setting. As well as allowing the device to be used stand-alone as a general purpose IO controller for example controlling lights, relays and switches, some other interesting possibilities exist.

For instance, it may be possible to connect the device to an SRAM con? The FPGA device would normally be un-con? Application notes, software and development modules for this application area will be available from FTDI and other 3rd parties. PreScaler Divide By 1 Fix The previous device had a problem when the integer part of the divisor was set to 1. In the 2nd generation device setting the prescaler value to 1 gives a baud rate of 2 million baud and setting it to zero gives a baud rate of 3 million baud.

Noninteger division is not supported with divisor values of 0 and 1. Though this does not eliminate the need for external decoupling capacitors, it signi? When the FTBL is being used without the con? For circuits requiring a long reset time where the device is reset externally using a reset generator I. This is the preferred con?

USB 2. Note : The device would be a USB 2. This allows multiple devices to be simultaneously connected to the same PC. Functional Block Descriptions 3. It requires an external decoupling capacitor to be attached to the 3V3OUT regulator output pin.

It also provides 3. However, external circuitry requiring 3. The output drivers provide 3. In accordance to the USB 2. Handshaking, where required, is handled in hardware to ensure fast response times. It can also be used to reset other devices.

This allows a blank part to be soldered onto the PCB and programmed as part of the manufacturing and test process. In this case, the device will not have a serial number as part of the USB descriptor.

For 6MHz operation no resistor is required. Tri-State during device reset. Tri-State during device reset, else drives out. All of the other USB device descriptors are unchanged. Goes Low after the device is con? If not required, tie to VCC. Output of the internal Reset Generator.

This pin can also be driven by an external 6MHz clock if required. Puts device in I. Its prime purpose is to provide the internal 3. When interfacing with 3. This package has a 7mm x 7mm body 9mm x 9mm including leads with leads on a 0. The above drawing shows the LQFP package — all dimensions are in millimetres. An alternative 5mm x 5mm leadless QFN32 package is also available for projects where package area is critical.

Part numeber for this version is FTBQ. The FTBQ is also a lead free package. See their seperate datasheets for package dimensions. Exceeding these may cause permanent damage to the device. The devices should be ramped up to a temperature of oC and baked for 8 to 10 hours.

This makes for an economical con? A value of 27pF is shown as the capacitor in the example — this will be good for many crystals and some resonators but do select the value based on the manufacturers recommendations wherever possible.

If using a crystal, use a parallel cut type. If using a resonator, see the previous note on frequency accuracy. In order to check for this condition, it is necessary to pull Dout high using a 10K resistor. Most available parts are capable of this. Check the manufacturers data sheet to? Some other parts have their pinout rotated by 90o so please select the required part and its options carefully. A typical con?

The value of the Ferrite Bead depends on the total current required by the circuit — a suitable range of Ferrite Beads is available from Steward www. To meet requirement a the 1. Failure to do this may cause some USB host or hub controllers to power up erratically. These pins have internal K pull-up resistors to VCCIO, so they will gently pull high unless driven by some external logic.

There are many such level converter devices available — this example uses Sipex SP devices which have enables on both the transmitter and receiver. This ensures that both the transmitters and receivers are enabled when the device is active, and disabled when the device is in USB suspend mode.

This example uses the Sipex SP device but there are similar parts available from Maxim and Analog Devices amongst others. It has separate enables on both the transmitter and receiver. RS is a multi-drop network — i. The RS cable requires to be terminated at each end of the cable. A link is provided to allow the cable to be terminated if the device is physically positioned at either end of the cable. In this example the data transmitted by the FTBL is also received by the device that is transmitting.

This is a common feature of RS and requires the application software to remove the transmitted data from the received data stream. A digital one-shot timer is used so that even a small percentage of data transfer is visible to the end user. Figure 12 shows a con? Another possibility not shown here is to use a 3 pin common anode tri-color LED based on the circuit in Figure 13 to have a single LED that can display activity in a variety of colors depending on the ratio of transmit activity compared to receive activity.

In this example, a discrete 3. VCCIO is connected to the output of the 3. For USB bus powered circuits some considerations have to be taken into account when selecting the regulator — a The regulator must be capable of sustaining its output voltage with an input voltage of 4.

These devices can supply up to mA current and have a quiescent current of under 1uA. Note : It should be emphasised that the 3. In such cases, no special care need be taken to meet the USB suspend current 0. As with bus powered 3. Switched 5v Power to External Logic 0. For external logic that cannot power itself down in that way, the FTBL provides a simple but effective way of turning off power to external circuitry during USB suspend.

Alternatively, a dedicated power switch i. A suitable power switch I. Please note the following points in connection with power controlled designs — a The logic to be controlled must have its own reset circuitry so that it will automatically reset itself when power is reapplied on coming out of suspend.

A high-power bus powered device must use this descriptor in the EEPROM to inform the system of its power requirements. Either connect the power switch between the output of the 3.

DSB Version 1. Updated 04 August Section 4. Updated 27 October Pin and package naming made consistent throughout data sheet.






PN-EN ISO 9001 LUTY 2009 PDF




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